Self-made capacitor boost circuit diagram scheme (1) circuit as shown below The integrated circuit IC1 is a timer, the output frequency is determined by the peripheral timing components R2 and C1, and the timing pulse outputted by the 3-pin is sent to the clock input terminal of the counter IC2. IC2 is connected into a six-way circuit, and the pulse train input from IC1 to the IC2CLK terminal is sequentially allocated to the Q0 to Q5 terminals of IC2. The transistors V1 to V5 are used to charge the capacitors C3 to C7, respectively, and the transistors V6 and V7 discharge the five capacitors C3 to C7 that have been charged. Since the voltages charged on C3-C7 are equal, a DC voltage of about 5 times the original charging voltage is obtained at the discharge output. The operating voltage of this circuit is provided by two parts:
The operating voltage of IC1 and IC2 is 9V, and the current consumption is very small. The other part can supply C~C7 charging voltage of 3~12V, and the DC voltage of about 15-50V can be obtained at OUT. Therefore, you can select the corresponding one according to your needs. The operating voltage gets the desired output voltage.
In the process of counting and outputting the IC2 from the Q0 to the Q5 terminals in sequence, V1 to V5 are sequentially gated, and the capacitors C3 to C7 respectively supply charging currents through the diodes D1 to D5, and sequentially charge C3 to C7. When the JC2 count is output to the Q5 terminal, V6 and V7 are both turned on, and the power supply is superimposed with the voltage on the charged C3 to C7 through the ce junction of V7, so that the DC terminal of the circuit obtains a DC voltage of about 5 times the charging voltage. . Since IC2 counts one cycle, capacitors C3 and C7 are charged and discharged once, and the OUT terminal of the circuit outputs a pulse. Therefore, when IC2 is continuously output, continuous pulse output can be obtained at the OUT terminal. After smoothing and filtering by the storage capacitor c8, it is continued. , stable DC voltage. It can be seen that the higher the counting frequency of IC2, the smoother the voltage obtained at the OUT terminal. Therefore, the output voltage characteristic of the OUT terminal can be improved by appropriately changing the operating frequency of IC1.
This circuit is a five-fold voltage output type, but it can also be set to 2-8 times voltage type according to the need. When connecting, IC2 can be set to 2~8 frequency dividing circuit, and 2~8 capacitors are sequentially charged through each triode. The voltage from each capacitor is discharged by the last transistor, and the voltage output of any voltage is obtained at the OUT terminal. When the output voltage of the OUT terminal is high, the withstand voltage of C3~C8 should also be increased accordingly, especially C8. In order to avoid breakdown.
Component selection In the figure, the transistors V1 to V5 are preferably Darlington transistors, and the resistance is 1/8W carbon film resistance. The 9V voltage for lC operation in the figure can be provided by a 9V stack battery, and the voltage of the voltage doubled can be provided by other power sources.
Circuit fabrication and debugging Two ICs can be installed using the lC socket, and the current consumption of the lC should be minimized under normal IC operation. The polarity of each charging capacitor cannot be reversed. After the production is completed, the power can be tested after careful inspection. This circuit can work normally after power-on, generally no debugging is required.
This circuit can also be used for DC boosting of the internal power supply.
Electronic voltage doubler and boost circuits have unique advantages in some portable electronic instruments because they eliminate the step-up transformers used in conventional boost circuits and replace them with integrated circuits and capacitors. This can reduce the weight of the instrument, and can also improve the conversion efficiency of the power supply. The circuit composition is shown in the figure. The circuit consists of a pulse oscillator, a pulse divider, a transistor switching circuit, a storage capacitor and an isolation diode.
Self-made capacitor boost circuit diagram scheme (2) The voltage doubler boost circuit composed of the gate circuit can provide the required high voltage working power for some electronic devices. Although the output current is not large enough, it is an economical and convenient power source for some circuits that require a sufficiently high voltage without requiring a large current. The circuit composition of this power supply is shown in the figure.
(a) is a voltage doubler circuit; (b) is a 5 voltage circuit.
Self-made capacitor boost circuit diagram scheme (3) 
The figure shows a crystal diode-capacitor ten times boost circuit. The circuit can be used as a DC voltage circuit such as an ozone generator or a combustion aid.
Self-made capacitor boost circuit diagram scheme (4) 
When the circuit is not powered, the level is 0V.
When power is on, the upper right corner +5V_ALWP charges C710, C722, C715, C719 through the 1 pin of D32. At this time, the potentials at both ends of the capacitor are as shown in the figure above. At this time, the actual level of the +15V_ALWP output port is 5V.
When the Y pin of U64 starts to output a square wave with amplitude of 5V, when Y is at 5V for the first time:
1. Since the voltage across the capacitor cannot be abrupt, the voltage across C715 is 5V on the left and 10V on the right. Then the current is charged to the C719 capacitor through the 2 pin of D35. After charging, the voltage of C719 rises to 10V.
2. At the same time, 5V of Y output also charges C710. The voltage across C710 is 5V on the left and 10V on the right. Then the current is charged to C722 through the 2 pin of D32. After the charge is completed, the voltage of C722 rises to 10V.
At this time, the actual level of the +15V_ALWP output port is 10V.
When the Y pin of U64 starts to output a square wave with amplitude of 5V, when Y is at 0V for the first time:
1. Since the potential across the capacitor cannot be abrupt, the voltage across C715 is 0V on the left and 5V on the right. When the voltage of C715 is 5V, C722 will charge C715 because C722 voltage 10V is greater than 5V of C715. After charging, C715=C722=7.5V. At this time, the voltage of C715 is still lower than the voltage of C719. However, since the D32 diode is reversed, the C719 will not charge the C715. The voltage of C719 is kept at 10V.
2. At the same time, the voltage of C710 is 0V on the left, 5V on the right, and the voltage on the left end of C722 is 7.5V. Due to the reverse cutoff of the 2 pin of D32, C722 will still not charge C710, and C722 will remain at 7.5V.
When Y is at 5V for the second time, C722 is charged to 10V through the 2 pins of C710 and D32. When Y is again low, C722 (10V) charges C715 (7.5V). The voltage of C715 becomes 8.75V. After several processes, the voltage difference across C715 rises to 10V. When Y is again 5V, the potential at the right end of C715 becomes 15V. Of course, throughout the process, the C715 is charging the C719 through the 2 pin of the D35.
Finally, the level of the +15V_ALWP output port becomes 15V.
Self-made capacitor boost circuit diagram scheme (5) This boost circuit uses only four components for an infinite boost.
The principle is shown in Figure 1. Connect the circuit of Figure 1 to the AC power supply with peak voltage E as shown in Figure 2.
The charging and discharging processes of the capacitors C1 and C2 at times t1-t4 are represented by Figs. 3a, b, c, and d, respectively. At time t1, the power supply charges C2 to E via D1; at time I2, the power supply and C2 charged to E charge C1 to 2E; at time t3, the power supply and C1 charged to 2E charge C2 to 3E. At time t4, the power supply and C2-charged to 3E charge C1 to 4E. Thus, the terminal voltages of C1 and C2 are sequentially incremented by E at times t5, t6, t7, and the like. During this period, the voltages dropped by Cl and C2 are all supplemented by D2 and D1, respectively.
In actual use, the boosted power supply can be output from one of C1 or C2. For details, refer to Figure 4. The capacity of C1 and C2 is determined according to the magnitude of the load current to meet the boosting requirement. Note that the load is never allowed to open during use, otherwise C1 and C2 will break down due to overvoltage.
